This invention relates to a method of controlling a frame-relay module, as well as a high-speed switching system. More particularly, the invention relates to a method of controlling a frame-relay module, as well as a high-speed switching system, in which predetermined processing is executed upon transmitting/receiving a control-information frame, via an ATM switch, between a control apparatus and the controller of a frame-relay interface circuit.
A frame relay (FR) is a transmission/switching technique suited to applications in which a large quantity of data is communicated in instantaneous fashion, namely applications in which data is communicated in bursts. A frame relay is especially suited to transmission/switching of data between LANs, which serve as fast busses. Further, since identification of a party in frame units and multiplex communication are realized, a communication line can be utilized very efficiently. More specifically, control information (a data link connection identifier, abbreviated to "DLCI") for identifying a frame is added to the header of an FR frame. Since a network is informed of a destination using the DLCI in each frame, frames having DLCIs of different values can be sent in continuous fashion, whereby a frame multiplex function is realized.
FIG. 8 is a block diagram illustrating a high-speed switching system having frame-relay modules. This is an example in which frames are transmitted via an ATM network. The system includes an ATM switch (ATM-SW) 11, an ATM terminal 12 and an ATM interface circuit (ATM-INF) 13. The ATM interface circuit 13 has a routing table (not shown). When an ATM cell enters the ATM interface circuit 13 from an incoming line 12', the circuit 13 replaces the VCI (virtual channel identifier) of the ATM cell based upon the routing table, adds routing information and then sends the ATM cell to the ATM switch 11. Further, the ATM interface circuit 13 removes routing information that has been added to an ATM cell inputted from the ATM switch 11 and then outputs the ATM cell to the line 12' on the side of the ATM terminal.
An ATM signaling unit (SIG) 14 is provided in the exit port of the ATM switch 11, and a processor (CC) 15 executes call processing as well as other processing. A bus line 17 connects the SIG 14 and the CC 15. A serial interface circuit (SSR) 18 allows a serial exchange of data with an FR interface circuit, described later. Each ATM terminal 12 (only one is shown in FIG. 8) is set beforehand to a signal VCI. In addition, the routing table within the ATM interface 13 is set to routing information, in correlation with the signal VCI, for routing a cell having this VCI to an outgoing line 14'.
When the ATM terminal 12 performs a call operation for calling a terminating terminal, a cell assembling unit within the ATM terminal 12 subdivides data, which includes the originating number, the terminating number, the type of terminal and attributes, etc., into cell units, produces a signal cell upon attaching a signal VCI to each item of subdivided data and applies the signal cell to the ATM interface 13. The latter adds routing information, which is for routing the cell to the outgoing line 14', and then sends the cell to the ATM switch 11. When the signal cell is sent to the ATM switch 11, the latter routes the signal cell to the outgoing line 14' based upon the routing information, whereby the signal cell is fed into the signaling unit 14. Upon receiving the signal cell, the signaling unit 14 assembles (forms into a frame) the information contained in the signal cell and informs the processor 15. The latter executes call processing such as caller service analysis, billing processing and terminating-numeral translation processing. The processor 15 also decides a virtual path identifier (VPI) and virtual channel identifier (VCI) and sends connection information, which includes the originating number, the terminating number, the VPI, VCI and other data to a trunk ATM exchange (not shown) via a signal network (not shown). The trunk exchange subsequently performs similar processing. A path to the ATM exchange to which the terminating terminal has been connected is eventually established and the data cell from the ATM terminal 12 is transmitted to the ATM terminal on the terminating side via the path established.
Numerals 21a, 21b, 21c . . . denote fast busses, e.g., LANs (local area networks), and numerals 22a, 22b, 22c, . . . denote FR routers (R). Each FR router refers to an internal protocol address (IP address) contained in the frame sent from the terminal accommodated by the LAN, obtains the DLCI and adds the DLCI to the frame. Further, the FR router eliminates the DLCI attached to a frame that enters from the side of a frame-relay module, described later, and outputs the frame to the LAN side.
Numerals 31, 32 . . . denote frame-relay modules provided between the FR routers and the ATM switch 11. The frame-relay modules are identically constructed. Each module includes frame-relay interface circuits (FR-INF) 41, 42 . . . . Each FR-INF adds logical-path information to the frame that enters from the FR router (R). Further, each FR-INF accepts a frame sent to it via the ATM switch 11 and sends the frame to the FR router. A fast bus 51 interconnects the plurality of FR interface circuits 41, 42, . . . , each of which is assigned a predetermined port address (PA). A bus controller (BC) 52 performs contention control (control of the right to use the bus) of the bus, a buffer (assigned a port address 0) 53 is connected to the fast bus 51, and a CLAD (cell assembly/disassembly) circuit 54 assembles a frame into a cell and disassembles an ATM cell into a frame. An ATM interface circuit 55 replaces the VCI of an ATM cell that has entered from the CLAD circuit 54, adds routing information to the cell and inputs the cell to the ATM switch 11. Further, the ATM interface circuit 55 eliminates routing information from an ATM cell that has entered from the ATM switch and then inputs the cell to the CLAD circuit 54.
The FR interface circuits 41, 42 are constructed as shown in FIG. 9. Specifically, each FR interface circuit includes a bus interface 61, a reception buffer (B-BF) 62, a transmission buffer (S-BF) 63, a transmitter/receiver (T/R) 64 for performing an exchange of frames with the FR router, a processor (CTL) 65, a direct memory access controller (DMA) 66, a memory (M) 67, a serial interface circuit (SSR') 68 and a bus 69. A logical-path setting table LPT is stored in the memory 67.
As shown in FIGS. 10(a), (b), the logical-path setting table LPT has a first table LPT.sub.1 showing the correlation between DLCI values appended to frames entered from the FR router and logical path data (PA, VPI/VCI, DPA, LA), and .noteq. a second table LPT.sub.2 storing the correspondence between link addresses LA, which contained in frames sent from a party via the ATM switch, and DLCI values.
In the first table LPT.sub.1, "PA" represents the port addresses (the port address of a buffer is 0) of the FR interface circuits 41, 42, . . . and buffer 53 within a frame-relay module on the originating side; "VPI/VCI" represents a virtual path identifier/virtual channel identifier; "DPA" represents a destination port address specifying an FR interface circuit within a frame-relay module at the destination; and "LA" represents internal information (link address) which, when a frame has reached a party, is for achieving linkage with regard to the particular DLCI value to which a conversion is to be made. In the second table LPT2, "LA" represents a link address contained in a frame sent from a party via the ATM switch.
In a case (intra-FRM connection) where a frame is transmitted to another LAN without the intermediary of the ATM switch 11, VPI/VCI and DPA corresponding to the DLCI value of the frame are both made 0 (see , .noteq.) and the port address PA is made a port address #a, #b, . . . of the FR interface circuit corresponding to the LAN of the frame destination. On the other hand, in a case (external FRM connection) where a frame is transmitted via the ATM switch 11, the port address PA is made 0 (port address of buffer 53).
When the processor 65 receives a frame with an attached DLCI value from the FR router, the processor 65 refers to the first table LPT.sub.1 to obtain the logical path data, removes the DLCI of the frame, adds the logical path data obtained and then transmits the frame. More specifically, in the case of the intra-FRM connection, as shown in FIG. 11(a), solely the port address PA and link address LA are added on. In the case of the external FRM connection, as shown in FIG. 11(b), the port address (=0), VPI/VCI, destination port address DPA and link address LA are added on.